A Path Dependency Graph for Verilog Program Analysis
نویسندگان
چکیده
In this paper, we present a path dependency graph for Verilog-HDL programs called path sequence. This path sequence can be used in static analysis based techniques, such as program slicing, and model abstraction as well as in functional test generation. We have implemented this graph inside a model reduction tool. It enhanced the capability of the tool without adding significant timing overhead.
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